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Layout Techniques for Integrated Circuit Designers
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Layout Techniques for Integrated Circuit Designers
Layout Techniques for Integrated Circuit Designers
商品＃: 131974209

Layout Techniques for Integrated Circuit Designers

商品＃: 131974209

TWD 5803

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Shop Layout Techniques for Integrated Circuit Designers online at a best price in Taiwan. 1630819107
  • This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today’s manufacturing techniques and how they impact design rules. You will understand how to build common high frequency devices such as inductors, capacitors and T-coils, and will also learn strategies for dealing with high-speed routing both on package level and on-chip applications. Numerous algorithms implemented in Python are provided to guide you through how extraction, netlist comparison and design rule checkers can be built. The book also helps you unravel complexities that effect circuit design, including signal integrity, matching, IR drop, parasitic impedance and more, saving you time in addressing these effects directly. You will also find detailed descriptions of software tools used to analyze a layout database, showing you how devices can be recognized and connectivity accurately assessed. The book removes much of fog that often hides the inner workings of layout related software tools and helps you better understand: the physics of advanced nodes, high speed techniques used in modern integrated technologies, and the inner working of software used to analyze layout databases. This is an excellent resource for circuit designers implementing a schematic in a layout database, especially those involved in deep submicron designs, as well as layout designers wishing to deepen their understanding of modern layout rules.
Publisher Artech House
Publication date 31 Aug. 2022
Edition Unabridged
Language English
Print length 463 pages
ISBN-10 1630819107
ISBN-13 978-1630819101
Item weight 930 g
Dimensions 18.42 x 2.54 x 26.04 cm

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Layout Techniques for Integrated Circuit Designers

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立即訂購並活動它 Monday, 十月 26

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